Particle Interconnect Stacked Die / Wafers

  1. Removable / reassemblable stacked die package
  2. Stacked wafers
  3. Products
  4. System In a Package (SIP)
  5. Competing non-remateable 3-D IC interconnects
  6. Reference
  7. DARPA 3D IC

Removable / reassemblable stacked die package

Removable / reassemblable stacked die package using Particle Interconnect

Patent 5,471,151 using existing die without modification. Unlike 3D wire bond die sizes are not important. Since dies are bonded at room temperature there is no induced thermal-mechanical stress.

Flex circuit interposers

Connecting two die. Connecting several die.
0.030" pitch 19x19 miniBGA socket. 0.050" pitch, 15x15 through-hole BGA socket.

Heat exchanger

Microchannel heat exchanger

Stacked wafers

Silicon-on-sapphire IC mounted on sapphire wafer

Stacked two 3" sapphire wafers. 0.001" line, 0.001" space, with integrated decoupling capacitor, and integrated active substrate in 1982, using specially developed sputtered fluxless hermetic interconnect.

Wafers before stacking Close up

Cyrogenic cooled vaccum isolated stacked wafers

Stacking of vacuum chamber, coolant chamber, PCB/MCM, and flipped chips.

Products

Particle Interconnect package

Advanced low-cost minimal IC package.

QFP 132 lead, 0.012" pitch OLB (Outer Lead Bond). Leadframe / Chip-On-Board socket & carrier.
  • 0.001"-0.005" flex/rigid board with flip chip attached topside (heat up/electrical down) {3 μ line & space on 3 μ flex obtainable at special labs}
  • Board acts as probe card/burn-in socket/final package, only bad die are thrown away at assembly.
  • Leads completely supported yet flexible and damage resistant.
  • Outer Lead Bond (OLB) attachment by conventional heated solder reflow method or non-heated Particle Interconnect methods.
  • Automatic or manual placement even with finest pitches.
  • Controlled impedance routing from OLB to die pad in either single or multi-layer PCB.
  • Lower cost than etched/stamped leadframes or conventional flip chip techniques.

Particle Interconnect impression

Surface of PLCC J-Lead after 30,000 insertions. Surface finish of lead passed steam aging test.

Remateable interposer

Inexpensive remateable and flexible interposer for through-silicon vias.

How to make through-silicon vias

Tru-Si Technologies Through-Silicon Vias

... The contact holes are made in the front side of the wafer, and an insulating layer of oxide is added to separate the silicon from the metal. After all front side processing is over, the wafer is simply thinned until the contacts are exposed. The ADP process etches the oxide so the metal is exposed, but it etches the silicon faster, so that the silicon remains insulated from the contacts in a very robust process.


Flash animation:

Removable / reassemblable die Multichip Module - L/D/C

Competing non-remateable 3-D IC interconnects

Competing technologies are expensive and can not be disassembled and reassembled to remove defective parts.

Philip Garrou, MCNC Research & Development Institute, Research Triangle Park, N.C. -- 2/1/2005

...

3. Chip-in-polymer processes, such as that shown, have been developed by IMEC, Fraunhofer-Berlin and Fujitsu, among others. In such technologies, chips are thinned, embedded and interconnected in a thin-film/polymer matrix.

...

Wafer-to-wafer stacking is most practical for high-die-yielding individual wafer layers. Die-to-wafer bonding, where known good die (KGD) can be selected and bonded to KGD on the base wafer, is best suited for lower-yielding wafer layers.

...

A major limitation of the 3-D technology is alignment (best case now ±1-2 um), which currently limits this technology to global interconnect.

...

...

4. In the Fraunhofer-Munich process, KGD are remounted on a handle wafer and transferred all at once under pressure to the bottom wafer. This allows reflow of all the chips at once. When the eutectic bond is made, no further processing need occur on the top chip, thus eliminating exposure issues on the now non-planar surface.

...

So where does 3-D technology stand today? Remaining 3-D technology issues include:

. CAD tools for 3-D design, which are not widely available and not understood by a majority of design engineers.

. Thermal dissipation of heat from the stack.

. Yield that is exacerbated in wafer-to-wafer, stacking the need for common die size wafer-to-wafer alignment limitations, which has not yet achieved ± 1 um.

. Thermal-mechanical stresses induced by the post-device processing.

...

3D wirebond

Cadence Allegro Package Designer 3D modeler

Reference

DARPA 3D IC